In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of individual devices coupled together to perform a certain function. To actually fabricate this circuit in a semiconductor substrate the circuit must be translated into a physical representation, or layout, which itself can then be transferred onto the silicon surface. Again, computer aided design (CAD) tools assist layout designers in the task of translating the discrete circuit elements into shapes which will embody the devices themselves in the completed IC. These shapes make up the individual components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, metal interconnections, and so on. The software programs employed by these CAD systems are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. Often, these rules are determined by certain processing and design limitations. For example, design rules defining the space tolerance between devices or interconnect lines so as to ensure that the devices or lines do not interact with one another in any unwanted manner.
Design rule limitations are frequently referred to as critical dimensions. A critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between two lines. Consequently, the critical dimension determines the overall size and density of the IC. In present IC technology, the smallest critical dimension for state-of-the-art circuits is 0.5 microns for line widths and spacings.
Once the layout of the circuit has been created, the next step to manufacturing the integrated circuit (IC) is to transfer the layout onto a semiconductor substrate. Photolithography is a well known process for transferring geometric shapes present on a mask onto the surface of a silicon wafer. In the field of IC lithographic processing a photosensitive polymer film called photoresist is normally applied to a silicon substrate wafer and then allowed to dry. An exposure tool is utilized to expose the wafer with the proper geometrical patterns through a mask by means of a source of light or radiation. After exposure, the wafer is treated to develop the mask images transferred to the photosensitive material. These masking patterns are then used to create the device features of the circuit.
An important limiting characteristic of the exposure tool is its resolution value. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose onto the wafer. Currently, the resolution for most advanced optical exposure tools is around 0.4 micron. Thus, the resolution value of present lithographic equipment is close to the critical dimension for most IC circuit designs. Consequently, the resolution of the exposure tool may influence the final size and density of the IC circuit. As the critical dimensions of the layout becomes smaller and approach the resolution value of the lithography equipment, the consistency between the masked and actual layout pattern developed in the photoresist is significantly reduced. Specifically, it is observed that differences in pattern development of circuit features depends upon the proximity of the features to one another.
Proximity effects in a lithographic process (using optical projection printing) can arise during imaging, resist pattern formation (exposure and development), and subsequent pattern transfer steps such as etching. The magnitude of the effect depends on the proximity or closeness of the two features present on the masking pattern. Proximity effects are known to result from optical diffraction in the projection system. This diffraction causes adjacent features to interact with one another in such a way to produce pattern-dependent variations.
For example, lines designed to have the same dimension, but which are placed in different proximity to other features in a layout (isolated vs. densely packed), will not have the same dimensions after being developed. Thus, a group of densely packed lines tends to transfer differently when compared with an isolated line. Obviously, significant problems can arise in an IC when line widths are not consistently reproduced.
Numerous methods have been developed to overcome the proximity effect problem. CD biasing is one method that has been developed to precompensate certain mask features so that the final target dimensions that are transferred to the wafer are consistent with non-compensated features. As an example, lines having the same width in a mask pattern can have different final resist line widths due to proximity effects. Specifically, it has been found that the final line width for isolated features is larger than that of packed features when utilizing positive optical photoresist. To reduce this inconsistency, IC manufactures designers have created mask patterns in which the original mask line width of the isolated features is smaller than the width of the packed feature. By pre-compensating the mask pattern, the final resist line widths for the isolated and packed features will be approximately the same. Normally, the amount of size increase or biasing is determined empirically and is highly dependent upon the exposure tool used, the type of resist process employed, and size of the critical dimension. Consequently, shifts from these nominal lithographical factors can easily have an adverse impact on the biased features. Therefore, this approach has not been widely adopted in the industry.
In the biasing approach it has also been found that increasing the thickness of the photoresist reduces the impact of the proximity effect caused by the resist process. As a result, at certain resist thicknesses the proximity effect can be minimized for a given exposure tool. The main drawback for varying resist thickness is that the selected resist thickness to produce minimum CD biasing is often not the desired thickness for accomplishing optimum resolution. Thus, CD biasing offers an unsatisfactory solution to proximity effect problems.
A multi-layer resist process is another method suggested for enhancing line width control and reducing proximity effects. This method involves coating a layer of relatively opaque material on top of a photoresist layer or alternatively, using a dyed planarizing layer to eliminate surface topography and reflectivity problems. Though reducing substrate reflectivity somewhat reduces proximity effects, none of the multi-layer resist processes currently in use entirely eliminates proximity problems, and are more expensive than conventional processes.
Still another prior art relies upon the known fact that the illumination coherency for the optical exposure tool can influence proximity effects. It has been recommended that less coherent illumination is more favorable for feature control. However, totally incoherent illumination often loses resolution causing the imaging process to be less than optimum. In addition, since most commercial exposure tools come with a fixed coherence setting, changing the coherency of the tool can be quite involved mechanically and is usually not recommended by the equipment vendor.
Finally, since it has been determined that the nature of proximity effects for electron beam (e-beam) imaging is opposite to that of optical imaging, it has been suggested that auto proximity compensation be utilized to reduce proximity effects. Auto proximity compensation is accomplished by using an e-beam generated 1X (no size reduction) reticle with an optical exposure tool, effectively cancelling out the proximity effects. However, there are many more benefits in applying a reduction exposure method as compared to a non-reduction technique. The most significant benefit is that as critical dimensions become smaller, mask venders are able to manufacture larger feature sized masks with a smaller percentage of errors than masks with smaller feature sizes. Additionally, dimension tolerances in the mask for the reduction exposure method are reduced by the amount of reduction during exposure. Since reduced dimension tolerances generates less device failures, the reduction method increases wafer yield. Consequently, the majority of IC makers today are utilizing a reduction method to produce wafers; making 1X technology less desirable for most applications. Further, auto proximity compensation is only beneficial in certain limited cases.
What is needed is a simpler less process dependent solution which solves the proximity effect problem. As will be seen, the present invention minimizes proximity effects by altering the masking pattern such that edge intensity gradients for isolated features match the edge intensity gradients for densely packed features. Once all features have similar edge intensity gradients, pattern transfer becomes more uniform, and the proximity effect problem is virtually eliminated.